數位電路的產物中，舉凡電腦、手機、家電產品等等，其中央處理器（CPU）扮演著非常重要的角色。隨著產品的複雜度和功能的多寡，CPU的處理速度也一直在提升，自管線式（Pipeline）架構被提出來以後，已成為高速處理器的主流。
本研究主要目的在於以HDL（Hardware Description Language）硬體描述語言，設計一顆具有五階層的Pipelined MIPS CPU，並針對管線中會發生的三大危障(hazard)：結構危障(structure hazard)、資料危障(data hazard)、控制危障(control hazard)，設計解決的機制，以增加CPU的效能。
設計結果經由ModelSim完成電路模擬後，下載至Xilinx Virtex XCV800 FPGA(Field Programmable Gate Array)驗證成功，完成整體設計架構，並加入周邊介面I/O電路設計和周邊顯示電路的實體連接，完成FPGA平台設計架構。最後，利用所設計的指令集撰寫相關程式，來驗證整個Pipelined MIPS CPU的運作。
本研究結果已成功完成一顆五階層的Pipelined MIPS CPU（包含浮點數指令），並解決三大危障等問題，總共實作了21道固定點指令、4道浮點指令。

Central processing unit in the now times plays a key essential role amid various logic circuit products. Due to demanding increasing complexity and enhanced function, CPU processing speed is requested to rapidly accelerate in
all the field with CPU inside such as computer, handset, home appliance etc.
The main purpose of this reserach is to design a five stages pipelined MIPS CPU with hardware description language to resolve structure, data and control three major hazards in pipeline system, design resolution mechanism and increase CPU efficiency.
The research is verified by that the simulated circuit and downloaded to Xilinx Virtex XCV800 FPGA. After downloading, then connect the relating circuit designing and the physical circuit to display on the 20×20 LCD.When the stage is ok, the whole FPGA structure is down. Finally I test the Pipelined MIPS CPU by the relate command. The research is including twenty-one fixed instructions and four floating instructions.

[1] A. A. Sagahyroon, “From AHPL to VHDL: a course in hardware description languages,” Education, IEEE Transactions on, Volume: 43, Issue: 4, Nov. 2000. Pages: 449 – 454.
[2] CIC reference, “Cell-Based IC Design Concepts, ” 2003.
[3] DIGITIMES Inc. “Homepage,” http://www.digitimes.com.tw.
[4] ECE/CIS Labstaff. “Homepage,” http://www.eecis.udel.edu/.
[5] Golden, M., Mudge, T. ”Comparison of two common pipeline structures” Computer and Digital Techniques, IEE Proceedings, Volume: 143, Issue: 3, Pages: 161 – 167, 1996.
[6] J. Smith. Douglas, “HDL Chip Design,” HDL Modeling Capability p.10, picture 1.5: Doone Publications. Madison, AL, USA, 1996.
[7] Kab Joo Lee, “Fault sensitivity analysis of a 32-bit RISC microprocessor,” VLSI and CAD, ICVC ’99. 6th International Conference, pp.529-532, 1999
[8] Kishore Kota, Joseph R. Cavallaro, “Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors,” IEEE Transactions on Computers, Vol. 42, No. 7, pp. 769-779, July 1993.
[9] Liu Zhenyu, Qi Jiayue “Implementation of precise exception in a 5-stage pipeline embedded processor” ASIC, Proceedings. 5th International Conference on, Volume: 1, 21-24, Pages” 447-451 Vol.1, 2003.
[10] Mark Holland, “Harnessin FPGAs for Computer Architecture Education” A thesis submitted in partial fulfillment of the requirements for Master of Science In Electrical Engineerign, University of Washington, 2002.
[11] MIPS Corporation, http://www.mips.com.
[12] MIPS Corporation, ”MIPS32 Architecture For Programmers ─ Volume I : Introdouction to the MIPS32 Architecture”.
[13] MIPS Corporation, ”MIPS32 Architecture For Programmers ─ Volume II : The MIPS32 Instruction Set.
[14] MIPS Corporation, “MIPS32 Architecture For Programmers ─ Volume III: The MIPS32 Privileged Resource Architecture”.
[15] S. Palnitlear, “Verilog HDL,” Englewood Cliffs, NJ: Prentice-Hall, 1996.
[16] Thorntino, “Design of a Computer: The Control Data 6600”, Scott, Foresman, Glenview, IL, 1970.
[17] William Stallings, “Computer Organization & Architecture: Designing For Performance Sixth Edition,” Pearson Education, Inc.2003.
[18] David A. Patterson & John L. Hennessy，曾志光、鄭光近譯，“計算機組織與設計軟硬體介面 第二版”，碁峰資訊，2000。
[19] David A. Patterson & John L. Hennessy，陳中和譯，“計算機組織與設計軟硬體介面 第三版”，東華書局，2005。
[20] M. Morris Mano & Charles R. Kime，江昭皚、范丙林譯， “邏輯與計算機設計 第二版”，p. 545，東華書局，2000。
[21] 王振傑，“雙指令架構之嵌入式微處理器的設計與實作”，成功大學電腦與通信工程研究所碩士詅文，2005。
[22] 林容益，“CPU/SOC及週邊設計與展實作（FPGA/CPLD）”。全華科技圖書有限公司，2003。
[23] 林瑛萍，“CPU設計與教學之FPGA硬體平台製作-以MIPS為例” ，台灣師範大學工業教育所碩士論文，2003。
[24] 林傳生，“使用VHDL電路設計語言之數位電路設計”，儒林圖書公司，2000
[25] 胡登貴，“結合CORIC演算法之MIPS CPU設計與實作” ，台灣師範大學機電科技學系碩士論文，2007。
[26] 施福基，“可合成似MIPS微處理器之涅合模式設計”，大葉大學電機工程學系碩士論文，2005。
[27] 黃文吉，“VHDL基本程式寫作及應用”。儒林圖書公司，2002。
[28] 鄭信源，“VHDL數位電路設計—基礎篇”。儒林圖書公司，2003。
[29] 鄭信源，“VHDL數位電路設計—進階篇”。儒林圖書公司，2003。